DISCRETE COSINE TRANSFORMS
- Research Paper. New Hardware-Efficient Algorithm and Architecture for the Computation of 2-D DCT on a Linear Systolic Array. Paper in PDF.
- Research Paper. A Systolic Array Architecture for the DCT. PDF.
- Combined LNS Adder/Subtractors for DCT Hardware. PPT slides. LNS - logarithmic number systems.DCT. Combined LNS adder/subtractor.
- Survey of DCT implementations. Example Implementation. PPT slides.
- Good research paper from 2005. PDF. Systolic Algorithms and a Memory-Based Design Approach for a Unified Architecture for the Computation of DCT/DST/IDCT/IDST.
No comments:
Post a Comment